When a digital logic signal is coupled from a sending circuit to a receiving circuit, the signal can be corrupted by distortion, often referred to as glitches. A glitch can cause the signal to cross the threshold between a logic 0 and a logic 1, causing the value of the signal to be misinterpreted by the receiving circuit.
Conventional de-glitch circuits typically remove glitches from a digital input signal by requiring a change in the input signal to persist for at least a predetermined time period, referred to as the de-glitching period, before the change is propagated to the output of the de-glitch circuit. Such a de-glitch circuit is disclosed in U.S. Pat. No. 6,778,111 issued Aug. 17, 2004 to Zhu et al.
However, this type of de-glitch circuit has the disadvantage of delaying the input signal by a time greater than or equal to the predetermined de-glitching period. Some digital logic circuits will not operate correctly if their input signals are subject to such delay.
Therefore, a need exists for a de-glitch circuit that removes glitches from a digital input signal without delaying the signal by the duration of the de-glitching period.